Conventionally, semiconductor memory devices such as flash memories have been fabricated by two-dimensionally integrating memory cells on the surface of a silicon substrate. In this type of semiconductor memory device, reduction of cost per bit and increase in memory capacity require increase in the packaging density of memory cells. However, recently, such increase in packaging density has been difficult in terms of cost and technology.
Methods of stacking memory cells for three-dimensional integration are known as techniques for breaking through the limit to increase in packaging density. However, in the method of simply stacking and processing layer by layer, increase in the number of stacked layers results in increasing the number of processes and increasing cost. In this context, the following technique is proposed. Electrode films made of silicon and insulating films made of silicon oxide are alternately stacked on a silicon substrate to form a stacked body. Then, through hole are formed in this stacked body by collective processing. A block insulating film, a charge storage film, and a tunnel insulating film are deposited in this order on the side surface of the through hole. Furthermore, a silicon pillar is buried inside the through hole (for instance, refer to JP-A 2009-146954 (Kokai)).
In this collectively processed three-dimensional stacked memory, a memory cell transistor is formed at each intersection between the electrode film and the silicon pillar, and information can be stored by controlling the potential of each electrode film and each silicon pillar to transfer charge between the silicon pillar and the charge storage film. In this technique, through holes are formed by collectively processing the stacked body. Hence, increase in the number of stacked electrode films does not result in increasing the number of lithography processes, and cost increase can be suppressed.
However, in such a collectively processed three-dimensional stacked memory, it is difficult to form memory cell transistors with the characteristics being uniform throughout the stacked body. For instance, when a through hole is formed in the stacked body, it is extremely difficult to process completely vertically the side surface of the portion piercing the insulating film, and a certain taper angle inevitably occurs. In particular, it is difficult to process a silicon oxide film. Hence, the through hole is narrower in the lower portion of the stacked body than in the upper portion. This causes variation in the characteristics of memory cell transistors.